Sammendrag
Abstract Rapid technology scaling has increased the requirements for analog techniques, due to ever-decreasing threshold voltage and power consumption. This thesis will present a proof-of-concept VCO-based ADC which uses a highly linear feedforward VCO with a ripple counter. The VCO-based ADC is modeled and simulated, both pre-layout and post-layout. The ADC has also been produced in TSMC180nm, taped out, and measured. The proposed VCO, which is a feedforward VCO, has a slope of 1.77 MHz/10mV, a linear input region of 0.45V, an dynamic range of 9.3, a maximum frequency of 89.3MHz, an average INL of 1.33MHz and an average DNL of 0.47MHz.