Ultra-Low-Voltage and Energy-Efficient Circuit Techniques for iOTs

Abstract

The main aim of this research is to study and develop new Ultra-Low Voltage and energy-efficient circuit techniques for low power iOT applications. In the digital domain, NP-domino logic technique is studied for relatively high-speed applications while using a power supply as low as 300 mV and below. Semi-Floating Gate technique is used to increase the speed of the conventional domino logic circuits for both single-rail and dual-rail NP-domino configurations. A chip prototype that includes SFG ULV inverter logic gates was also fabricated and successfully measured. The intent was to study the practical challenges of the logic. In the analog domain, energy-efficient circuit techniques are studied for the iOT s. For the LCD displays in iOT devices, a high-speed and energy-efficient buffer amplifier is proposed. Finally, an energy-efficient, successive approximation register analog to digital converter is designed, fabricated and measured during this research, which is suitable for ultra-low-power iOTs. Several techniques have been used to reduce the power consumption. The proposed data converter is powered up by a simple energy harvester in the lab. Utilizing lower supply voltages, minimizing the static currents, designing circuits with different threshold voltages, sleep mode designing, and minimizing leakage currents were the techniques that employed.