Reducing Power Dissipation while increasing Yield and Defect-Tolerance in Subthreshold CMOS

Abstract

This thesis addresses some of the key aspects of reducing both static and dynamic power consumption in digital circuits, by operating the circuits in the subthreshold region, and at the same time retaining acceptable levels of both yield and defect-tolerance. Through evaluation of six different Full Adder structures, it is shown that static-based implementations are most promising for subthreshold operation, providing the best tradeoff between speed and power, reaching operating speeds of 2 MHz and average power dissipation in the area of 1 nW for VDD = 200 mV. Furthermore, both static and dynamic regulation techniques are addressed, coping with variation in temperature and process parameters, intra-die mismatch and device defects. A novel technique for static regulation improving gate symmetry is presented, where regulators structurally similar to the logic gate in question is utilized for controlling the logic gate's bulk/back-gate. A simple scheme for employing gate-level redundancy is also explored, where two or more identical logic gates are operated in parallel, with short-circuited outputs. Employing this output-wired redundancy scheme for a Mirrored minority-3 static CMOS gate, results in a tentative lower limit of VDD = 175 mV and R = 2, to be able to achieve reliable operation and yield in the face of transistor mismatch.