Multiple-Input Common-Gate FGUVMOS Transistor and Its Application in Multiple-Valued Logic Circuits

Abstract

The demand for reduced area and power consumption have usually been met with improvements in processing techniques, allowing for increased integration and a reduction in the power supply voltage. Some technology improvements have also occurred, such as strained silicon and silicon-on-insulator. But some design techniques also feature a significant reduction in area and power consumption, such the asynchronous design approach. Reducing the amount of interconnects is another approach, for which multiple-valued logic might be an ideal candidate.

This thesis explores the multiple-input common-gate FGUVMOS transistor and the design of multiple-valued logic circuits using this transistor. We examine in detail a UV-programming technique for initializing the floating-gate. There is no need for any extra programming circuitry with this programming method, since it utilizes the supply rail of the nMOS transistor to place a charge on the floating-gate. An important benefit of the floating-gate initialization is a matching of the pMOS and nMOS transistor at a predetermined current level. We also look closer at some of the layout issues concerning FGUVMOS circuits.

We also explore a new area of application for the FGUVMOS transistor, namely multiple-valued logic. The main design parameter of the FGUVMOS transistor--the capacitive division ratios of the coupling capacitors to the floating-gate--is well suited for designing voltage-mode multiple-valued logic circuits. Several multiple-valued logic circuits are examined in detail and several design issues are addressed. Measurements on a fabricated chip are supplied, as well as simulations of the various circuits. And the voltage output functions for the presented circuits are also developed.