| dc.date.accessioned | 2013-03-12T08:10:02Z | |
| dc.date.available | 2013-03-12T08:10:02Z | |
| dc.date.issued | 2006 | en_US |
| dc.date.submitted | 2006-01-27 | en_US |
| dc.identifier.citation | Zhang, Fan. Low-power neural inspired parallel addition. Hovedoppgave, University of Oslo, 2006 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10852/9393 | |
| dc.description.abstract | I introduced a new circuit derived from a real-time reconfigurable perceptron, called “Output-Wired Inverter structure” (“OWIS”) which operates under low energy conditions into a Kogge-Stone adder in order to characterize the output efficiency in both 16 and 32-bit systems. The results would be compared to the Kogge-Stone adder which is built by “mirror structure” (“MS”). | nor |
| dc.language.iso | eng | en_US |
| dc.title | Low-power neural inspired parallel addition : application in kogge-stone adder | en_US |
| dc.type | Master thesis | en_US |
| dc.date.updated | 2006-04-27 | en_US |
| dc.creator.author | Zhang, Fan | en_US |
| dc.subject.nsi | VDP::420 | en_US |
| dc.identifier.bibliographiccitation | info:ofi/fmt:kev:mtx:ctx&ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft.au=Zhang, Fan&rft.title=Low-power neural inspired parallel addition&rft.inst=University of Oslo&rft.date=2006&rft.degree=Hovedoppgave | en_US |
| dc.identifier.urn | URN:NBN:no-11629 | en_US |
| dc.type.document | Hovedoppgave | en_US |
| dc.identifier.duo | 35642 | en_US |
| dc.contributor.supervisor | Snorre Anuet | en_US |
| dc.identifier.bibsys | 060708727 | en_US |
| dc.identifier.fulltext | Fulltext https://www.duo.uio.no/bitstream/handle/10852/9393/5/Zhang2.pdf | |