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dc.date.accessioned2013-03-12T07:58:20Z
dc.date.available2013-03-12T07:58:20Z
dc.date.issued2003en_US
dc.date.submitted2003-08-25en_US
dc.identifier.citationRiis, Håvard Kolle. Multi-level static memory for on-chip learning. Hovedoppgave, University of Oslo, 2003en_US
dc.identifier.urihttp://hdl.handle.net/10852/8934
dc.description.abstractThis thesis investigates different memory types for use as a synaptic storage in a neuromorphic application for on-chip learning. Our main concern was to find a suitable implementation four this purpose. We were looking for a memory element which could be used as a distributed storage with no external control signals or backup. This memory should preferably be analog, which excludes the common digital storage techniques such as latches and flip-flops. Dynamic multi-level or analog memory will also be insufficient, since it requires an external storage with AD/DA converters to preserve its multi-level or analog value. Furthermore, the value stored should be easily altered. Previous work has used floating gate(FG), which has many advantages in a neuromorphic design, i.e. permanent storage, slow learning and infinite resolution. However, there are severe device property mismatches and specialized initialization and programming techniques are required to alter the value stored. After initial investigation and searches for relevant implementation, no optimal solutions where found, and we decided to test a novel memory element which is presented in this thesis. It is a multi-level memory, which stores an analog value over a short period of time. The memory preserves its own state through a local feedback path, and does not require external control signals. The value is easily altered by directly applying a voltage, or as done in this thesis, by injecting or drawing a current. We start with an introduction to neuromorphic electronics and different analog an multi-level memory. We then present the objective of the thesis and basic theory. Next, a presentation of the different circuit componenets with test results are given. Last, the implemenetation is discussed and future work is proposed.nor
dc.language.isonoben_US
dc.titleMulti-level static memory for on-chip learningen_US
dc.typeMaster thesisen_US
dc.date.updated2003-10-24en_US
dc.creator.authorRiis, Håvard Kolleen_US
dc.subject.nsiVDP::420en_US
dc.identifier.bibliographiccitationinfo:ofi/fmt:kev:mtx:ctx&ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft.au=Riis, Håvard Kolle&rft.title=Multi-level static memory for on-chip learning&rft.inst=University of Oslo&rft.date=2003&rft.degree=Hovedoppgaveen_US
dc.identifier.urnURN:NBN:no-6880en_US
dc.type.documentHovedoppgaveen_US
dc.identifier.duo12875en_US
dc.contributor.supervisorPhilipp Hafligeren_US
dc.identifier.bibsys031724507en_US
dc.identifier.fulltextFulltext https://www.duo.uio.no/bitstream/handle/10852/8934/1/hoppgavehkriis.pdf


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