Low Power CMOS Design : Exploring Radiation Tolerance in a 90 nm Low Power Commercial Process

Abstract

This thesis aims to examine radiation tolerance of low power digital CMOS circuits in a commercial 90 nm low power triple-well process from TSMC. By combining supply voltage scaling and Radiation-Hardened By Design (RHBD) design techniques, the goal is to achieve low supply voltage, radiation tolerant, circuit behavior. The target circuit architecture for comparison between different radiation hardening techniques is a Successive Approximation Register (SAR) architecture comprising both combinational and sequential logic. The purpose of the SAR architecture is to emulate a larger system, since larger systems are usually composed of combinational and sequential building blocks. The method used for achieving low power operation is primarily voltage scaling, with the ultimate goal of reaching subthreshold operation, while maintaining radiation tolerant circuit behavior. Radiation hardening is performed on circuit-level by applying RHBD circuit topologies, as well as architectural-level mitigation techniques. This thesis includes three papers within the field of robust low power CMOS design. Two of the papers cover low power level shifter designs in 90 nm and 65 nm process from STMicroelectronics. The third paper examines memory element design using minority-3 gates and inverters for robust low voltage operation. Prototyping has been conducted on low power CMOS building blocks including level shifter and memory design, for potential use in future radiation tolerant designs. Prototyping has been conducted on two chips from two different 90 nm processes from STMicroelectronics and TSMC. A test setup for radiation induced errors has been developed. Experimental radiation tests of the SAR architectures were conducted at SAFE, revealing no radiation induced errors.