RISC-V Processor Core Customization and Verification for m-NLP Applications

Abstract

This work experimented with using a custom instruction set extension for computing electron density from sensor data received from a multi-needle langmuir probe (m-NLP). Custom instructions were designed and implemented on a RISC-V processor core. The aim being to both speed up the computation and to reduce transmission data, in order to increase spatial resolution and overcome limitations of the communications downlink. The central stategy is to use a small core with specialized acceleration instead of a bigger core with excess features, in order to meet the m-NLP project's potential future of fitting a processor on the same die as other electronics. An attempt was also made to use plain integers for computations, while other theses have used floating point numbers either on an FPU (floating point unit) or using software emulation. Emphasis is placed on verification of the implemented design, using tools like the universal verification methodology (UVM) and SystemVerilog assertions (SVA). Precision of the results, speed of computation, and size of output data was found to either improve upon or match that of previous work. It was found that the precision of the results are marginally within acceptable limits given the range of electron densities of interest. Precision measurements were done both against real data from an ICI-2 sounding rocket and generated stimuli. By measuring the cycle count of computations, it was possible to compare the speed of different implementation. In this case it was found that with the new modifications, the time to compute electron density is in fact reduced from a pure C language implementation and even more so compared to emulated floating point. The reduction in data transmission achieved by previous theses was maintained. It now requires a 29-bit integer per sampling, instead of 64 bits of raw data, being slightly lower than 32-bit floating point numbers. It was found that even with the timing paths introduced by the new extension, computations can be done on FPGA at 14 times a desired sampling rate of the m-NLP system.