Cache Behaviour in Multi-/Many-Core Environment: N-Core Configurable Cache Simulator Performance Evaluation

Abstract

The rapid increase in the number of processors demands quicker and more reliant data availability to avoid extensive memory accesses. Caches hierarchies are most important in an efficient n-core system. However, more processors often imply more complexity in cache design. This thesis investigates various cache configurations in single-, multi- and many-core environments with a cache simulator developed for this thesis. The cache simulator is a highly configurable n-core simulator implemented with the MESIF cache coherency protocol. Over various configurations, some of the results include findings such as rapid increase in the occurrence of thrashing increasing with the number of cores and the relationship between compulsory misses, coherence misses and block size. Furthermore, the thesis investigates how various configurations can reduce the number of false sharing misses. The results are indicating a possible solution to the problem, but at the cost of an increasing number of compulsory misses.