Improvements towards Optimal Design of Reliable Subthreshold Digital CMOS with applications in Logic and Memory

Abstract

This dissertation is organized as a collection of papers, where each paper represents original research contributions relating to the design and analysis of ultra low power CMOS, with a particular emphasis on ultra low voltage and subthreshold operation. The individual papers represent advancements particularily within methods and practices related to the design of both digital logic and memory circuits in the presence of severe process variation. At the device level it is demonstrated how the use of multiple minimum-width gates can exploit the inverse narrow-width subthreshold device effect to improve performance and power-delay products. Measurement results from a 90 nm prototype confirm the effect. Multi-objective optimization strategies are developed and applied to allow exploration of the Pareto optimal design space for reliable logic at 150mV. Targeting operation at 300mV, the design of a 9-transistor SRAM memory cell employing multi-Vt and virtual power techniques is presented. A multi-objective optimization strategy is developed and applied to achieve an optimal trade-off for an efficient and reliable sizing of the SRAM cell. Based on the 9-transistor cell, measured results from an ultra low voltage 64 × 32 SRAM module operating down to 273mV in a 65 nm technology indicate good yield and competitive performance metrics (17.8 fJ/access/bit at averages of 761 kHz @ 321mV supply). Finally, the behavior of subthreshold logic circuits under the influence of adverse fluctuations in the transistor threshold voltages is treated analytically, with specific emphasis on minimum-energy operation and yield constraints. The analysis can suggest optimal choices for supply voltage and device sizing, prior to simulation.