Two-Phase Dynamic Ultra-Low Voltage VLSI Digital Design

dc.contributor.author	Mo, Alexander
dc.date.accessioned	2015-02-09T23:01:43Z
dc.date.available	2015-02-09T23:01:43Z
dc.date.issued	2014
dc.identifier.citation	Mo, Alexander. Two-Phase Dynamic Ultra-Low Voltage VLSI Digital Design. Master thesis, University of Oslo, 2014
dc.identifier.uri	http://hdl.handle.net/10852/42135
dc.description.abstract	A new logic style named Two-Phase Dynamic Ultra-Low Voltage (TP-DULV) logic is developed. The new logic style uses the increased gate voltage swing from the ULV FG technique and introduces a new concept for ensuring a higher tolerance against random process variations when operating at ultra-low voltage supplies.	eng
dc.language.iso	eng
dc.subject	Ultra
dc.subject	Low
dc.subject	Voltage
dc.subject	Digital
dc.subject	Design
dc.subject	dynamic
dc.subject	logic
dc.subject	floating
dc.subject	gate
dc.subject	logic
dc.subject	PVT
dc.subject	variations
dc.subject	at
dc.subject	low
dc.subject	voltages
dc.subject	duty
dc.subject	cycled
dc.subject	systems
dc.subject	low
dc.subject	power
dc.subject	digital
dc.subject	design
dc.subject	subthreshold
dc.subject	design
dc.title	Two-Phase Dynamic Ultra-Low Voltage VLSI Digital Design	eng
dc.type	Master thesis
dc.date.updated	2015-02-09T23:02:58Z
dc.creator.author	Mo, Alexander
dc.identifier.urn	URN:NBN:no-46556
dc.type.document	Masteroppgave
dc.identifier.fulltext	Fulltext https://www.duo.uio.no/bitstream/handle/10852/42135/1/Two-Phase-Dynamic-Ultra-Low-Voltage-Digital-Design.pdf

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