| dc.description.abstract | With system on chip (SoC) gaining popularity in RF-applications, the need for UWB LNAs with an acceptable area and power consumption has increased. An amplifier topology with promising wideband results is the distributed amplifier (DA). In this thesis, a 5-stage DA, 3- stage DA and cascaded DA optimized for SoC, are designed and fabricated in the TSMC 90nm CMOS process. The DAs are based on artificial transmission lines (ATL), as opposed to real transmission lines, in order to save area. A normal practice has been to terminate the ATLs in half-sections in order to obtain a more flat group delay and better matching. In this thesis, half- section inductors have been substituted by direct terminations, except for the inputs, achieving both flat gain and area efficiency. The measured results show that the designed 5-stage DA and 3-stage DA have comparable specifications to other recently published DAs, while using less power and area. Moreover, the cascaded DA has large gain and bandwidth, but suffers from high distortion. The 5-stage DA provides a -3dB bandwidth of 36.5GHz and a S21 of 10.7dB ± 1.5dB, while consuming 24mA from a 1.2V supply and occupying an area of 0.67mm^2. The average noise figure and IIP3 are 7.4dB and 6dBm@10GHz. The 3-stage DA provides a -3dB bandwidth of 39GHz and a S21 of 8.8dB ± 2dB, while consuming 16mA from a 1.2V supply and occupying an area of 0.41mm^2. The average noise figure is 8.8dB and IIP3 is 7.9dBm@15GHz. Finally, the cascaded DA presents a -3dB bandwidth of 31.45GHz and a S21 of 18dB ± 3dB, while consuming 42mA from a 1.2V supply and occupying an area of 1.08mm^2. The average noise figure and IIP3 are 8.1dB and -2.2dBm@10GHz. | eng |