A System for Fast Dynamic Partial Reconfiguration using GoAhead : Design and Implementation

Abstract

Reconfigurable hardware in the form of Field Programmable Gate Arrays (FPGAs) was brought to market almost three decades ago, but many designs are still not using the full potential of the devices. By designing and implementing systems using partial runtime reconfiguration of the device, it is possible to achieve more efficient use of resources. For example, the impact of static power consumption could be reduced by using a PR design flow to make a FPGA design fit onto a smaller device.

The goal of this thesis is to design and implement an open-source system for partial reconfiguration (PR) using the GoAhead tool flow. This system is optimized for several different FPGA platforms that are based on many different Xilinx devices, including commonly used academic board. It is also designed to provide good reconfiguration speeds, since one of the biggest hurdles in PR is the overhead resulting from the reconfiguration time. This system can also act as a platform for further studies on PR by students and researchers interested in reconfiguration using the GoAhead framework.

The implemented system is built around a baseline MIPS CPU, designed particularly for this project. Reconfigurable custom instructions are added as an extension to the MIPS using GoAhead. Connected to the MIPS over the system bus is a configuration controller capable of writing configuration data to the device from both a host-PC and external flash memory. Furthermore, the implemented configuration controller has support for compressed bitstreams and module relocation. A large PR region with a streaming interface was implemented at the top of the device to allow for PR modules in the system.

The final system is capable of partial reconfiguration of custom instructions and PR modules. The use of custom instructions is observed to save 518 cycles compared to a software implementation of the same function. By using compressed bitstreams and a 100~MHz system clock, the configuration controller is able to produce a configuration data throughput of 97~MB/s directly from external flash memory. Furthermore, the configuration controller supports two-dimensional relocation without any CPU intervention during the configuration process.