An in depth examination of semi floating gate ultra low voltage flip-flops for high speed applications

Abstract

In this thesis 4 different ultra low voltage (ULV) flip-flops are presented. Floating gates has been exploited to significantly increase the drain-source current. This technique has proved to decrease the delay significantly and shown that these flip-flops can perform at high speed operations for near subthreshold voltages (300mV).

The ULV flip-flops proved to be faster, with a delay up to 20 times faster, than other flip-flop topologies presented in this thesis. The ULV flip-flops also proved to have very little setup and hold times.

With regards to yield, the ULV flip-flops proved to be better at higher frequencies, above 1MHz, than the other flip-flop topologies. One of the ULV flip-flops outperformed the others with a much better yield at all frequencies and supply voltages.

In terms of EDP the ULV flip-flops revealed very good properties. Overall the ULV flips-flops had significantly better EDP, at all frequencies and all supply voltages, than the comparison flip-flop.

One of the flip-flops has been selected for layout design. For the layout the floating gates have been implemented by using MIM capacitors to create crosstalk between two metal strips in the same layer. The layout design uses floating bulks by implementing deep n-wells and enclose the p-substrate for all nMOS transistors with n-wells. This way the p-substrates of all the nMOS transistors have been separated.

The simulations and layout presented in this thesis have been performed in Cadence TSMC 90nm CMOS process.