Abstract
Despite the fact that germanium played a significant role in the advent of modern electronics, silicon-germanium alloys have not been used or studied nearly as extensively as silicon. However, a recent resurgence in industrial and research interest in silicon-germanium ensures that it will have an increasingly important role in nano- and opto-electronics. It is unavoidable that a sound understanding of the oxidation of silicon-germanium will be required as processes are developed for using the material in electronic applications. In fact, a profound appreciation for the oxidation kinetics of silicon-germanium could itself create new applications for the material.
The present work investigates the use of thermal oxidation in nanostructuring of epitaxially grown silicon-germanium by examining the kinetics of oxidation and the redistribution of germanium at the oxidation interface. This is done for oxidations in dry O2 ambients with a particular focus on the influence of temperature and crystalline orientation on the post-oxidation germanium distribution. Physical characterization by x-ray diffraction and variable angle spectroscopic ellipsometry is used along with diffusion and oxidation modeling to derive a series of relations to describe the germanium content and layer thicknesses for the multiple layers created by oxidation. Both modeling and experimental results reveal that the germanium content at the oxidation front is strongly dependent on the oxidation temperature and only weakly dependent on the germanium content in the as-grown silicon-germanium layer. Evidence is presented showing that a decrease, rather than an increase, in the germanium content at the oxidation front may be achieved under certain conditions. The germanium content at the oxidation interface is used to discuss the potential for germanium to act as a catalyst or inhibitor for oxidation of silicon-germanium alloys. Taken together, germanium redistribution by thermal oxidation and the empiric relations presented here may be used to design process recipes for fabrication of nanostructures for nano- and opto-electronic applications.