| dc.date.accessioned | 2013-03-12T08:28:43Z | |
| dc.date.available | 2013-03-12T08:28:43Z | |
| dc.date.issued | 2009 | en_US |
| dc.date.submitted | 2009-09-01 | en_US |
| dc.identifier.citation | Eikeland, Erik. Nanoscale Double-Gate SRAM Design. Masteroppgave, University of Oslo, 2009 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10852/11263 | |
| dc.description.abstract | This work uses an extensive number of simulations to determine the usability
of DG MOSFETs in SRAM circuit design. The simulations have been carried
out in Silvaco ATLAS and MixedMode model and circuit simulation software.
Structures with gate lengths of 50 nm and 20 nm have been tested both
on their own and incorporated into larger circuitry, and these are showing
promising results. | eng |
| dc.language.iso | eng | en_US |
| dc.title | Nanoscale Double-Gate SRAM Design | en_US |
| dc.type | Master thesis | en_US |
| dc.date.updated | 2011-12-15 | en_US |
| dc.creator.author | Eikeland, Erik | en_US |
| dc.subject.nsi | VDP::430 | en_US |
| dc.identifier.bibliographiccitation | info:ofi/fmt:kev:mtx:ctx&ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft.au=Eikeland, Erik&rft.title=Nanoscale Double-Gate SRAM Design&rft.inst=University of Oslo&rft.date=2009&rft.degree=Masteroppgave | en_US |
| dc.identifier.urn | URN:NBN:no-26081 | en_US |
| dc.type.document | Masteroppgave | en_US |
| dc.identifier.duo | 94392 | en_US |
| dc.contributor.supervisor | Tor Fjeldly | en_US |
| dc.identifier.bibsys | 115006281 | en_US |
| dc.identifier.fulltext | Fulltext https://www.duo.uio.no/bitstream/handle/10852/11263/1/Masterxx1x.pdf | |