On a configurable hardware implementation of the BCJR algorithm

Abstract

The introduction of turbo codes in 1993 was a breakthrough in constructing error correction codes that were able to approach the theoretical limit of performance. Different implementations of turbo codes have become widely used in recent wireless communication systems. It is possible for hardware manufacturers to buy complete turbo decoding solutions as integrated circuits or IP (Intellectual Property) blocks, but these are usually tailor-made for a specific application. This thesis presents a parameterized hardware implementation of the turbo decoding algorithm, called a SISO module, that is generic (parameterized behavior and structure) and scalable. Thus, for each application a balanced decision can be made taking into consideration speed, complexity and power consumption. The proposed implementation can be used as a constituent decoder in parallel or serial turbo decoding networks, in a turbo equalizer or as a MAP decoder. A performance loss less than 0.08dB was accomplished for the fixed point implementation with short bit widths by an exploration of performance for different representation of external and internal signals and eliminating destructive saturation. An effort was made in exploring and combining the latest research available to reduce complexity and the signal path. The signal path through the decoder was shortened by implementing parallel circuits for all arithmetic operations of the algorithm, and simplifying or eliminating logic. The throughput for a turbo decoder based on the SISO IP was shown to be comparable to other recent implementations. The thesis work includes developing and optimizing a behavior model in ANSI C/ MATLAB, implementing the module in VHDL, testing, and synthesizing for ASIC and FPGA.