Simulation of Nanoscale CMOS

Abstract

Abstract - Device scaling is directly responsible for Moore’s law and has enabled remarkable improvements in CMOS (Complementary Metal-Oxide-Semiconductor) device performance. As device dimension shrinks, the channel resistance decreases, this in turn allows faster circuit operation. However, as the intrinsic device continues to improve, parasitic components such as the series resistance in the source/drain region start to limit device performance. Controlling these parasitic components, through proper design, are therefore essential. TCAD (Technology Computer Aided Design) can be an important tool that allows us to understand various design parameters on device performance. Furthermore, it allows the investigating of different internal quantities that are not available experimentally. This document presents the results of a thorough study of the scaling down the MOSFETs and its impact on the device performance. A major challenge is to maintain a good control of short channel effect in the low threshold voltage case. Moreover, high-field effects that are related to the increased electrical field in the channel owing to the reduction of the dimensions will be dominant for very small dimensions. The simulations are based on using a selected doping profile and oxide thickness according to channel length to cope with the variable specification of the ITRS (International Technology Roadmap for Semiconductor) in order to improve the device performance. The simulated results of the devices design at the 25 nm channel length generation are considered to be the most promising candidate for an excellent procedure in suppressing the short channel effects in the today’s technology. While the results and conclusions from this study are the main focus of this thesis, considerable attention is paid to the software that enabled the successful implementation of the study and processing of the simulation results.