Frequency Σ ∆ Modulator with ultra-low power supplies towards sub-100 mV

Abstract

This master thesis centers on the exploration of a frequency delta-sigma modulator (FDSM) with ultra-low power supply down to 80 mV for the analog circuitry. The FDSM is configured with ring voltage controlled oscillator (RVCO) serving as the integrator, and two D-flip flops with one as a counter and the other one as a register, finally a differentiator to separate the quantization error from the signal. All components are operated in the subthreshold region as they are supplied with voltages of 80 and 100 mV. Schmitt trigger based logic gates are employed in the entire circuit as the topology is proved to be operational and robust with ultra-low power supply in several sources. This design offers an unconventional solution to ultra-low power supply limitations, by employing an undersampling of the RVCO under an oversampling method of the overall system. Various simulation results are presented in this thesis, as well as the design choices and analysis of the output signal in both time and frequency domain. This design has the potential for applications such as biomedical devices for monitoring heartbeats and blood pressure, as well as sensor interfaces for self-powered IoT products.